Here's the 16-bit 8086 source to my bit mirror function, inputs are bx:dx
for the size (question wants 32 there) and dword [hhvar]
for the data to be bit-mirrored, output is in bx:dx
. Like vnp also suggested I use rcl
. I shift right bx:dx
and then rotate-with-carry-left into si:di
.
of_bit_mirror:
mov cx, dx
test bx, bx
jnz .large
cmp dx, byte 64
jb .normal
.large:
xor bx, bx ; mirror count 64 or higher:
xor dx, dx ; all 32 bits mirrored with (nonexistent) zero bits
retn
.normal:
mov dx, word [hhvar]
mov bx, word [hhvar+2]
cmp cl, 1
jbe .ret ; mirror count one or zero, return input -->
push si
push di
push cx
mov di, -1
mov si, di
.loopmask:
shl di, 1
rcl si, 1
loop .loopmask ; create mask of bits not involved in mirroring
and si, bx
and di, dx ; get the uninvolved bits
pop cx
push si
push di ; save them
xor si, si
xor di, di ; initialize mirrored register
.loop:
shr bx, 1
rcr dx, 1 ; shift out of original register's current LSB
rcl di, 1
rcl si, 1 ; into other register's current LSB
loop .loop
pop dx
pop bx ; restore uninvolved bits
or bx, si
or dx, di ; combine with mirrored bits
pop di
pop si
.ret:
retn
In relation to your exercise, this solution allows dynamically selecting the width of the bit mirror operation, so that the 8-bit example "if x == {01001111}_2, then the output is {11110010}_2" can be run by inputting 8 in bx:dx
and 0100_1111b = 4Fh in the variable.
I also decided to mask out the uninvolved (higher) bits and return them unchanged.
Both of my loops only have one branch for the loop itself each, whereas your loop's code branches quite a lot, including a conditional branch. Conditional branch prediction is a notoriously difficult part of the processor, so less branches are better. (Other answers also eliminated the conditional branch in several ways.)
Aside the conditional branch, you're also using an unconditional branch to now_rotate. This does not have the negative performance impact of a conditional branch, but it does make your solution be spaghetti code. The amount of labels you need (add_one) is another sign of spaghetti code. Here's how to reduce the spaghetti factor (while keeping the conditional branch):
shr eax, 0x1 ; Kick the right-most bit out ...
mov ebx, 0x0 ; Initialise register to a 0
jnc now_rotate ; If eax bit was a 0 jump to now_rotate
mov ebx, 0x1 ; Reset register to a 1
now_rotate:
This streamlines the control flow. However, if ebx
is initialised to zero then there is an easier way to get it to one. inc ebx
is (in 32-bit code segments) a one-byte opcode:
shr eax, 0x1 ; Kick the right-most bit out ...
mov ebx, 0x0 ; Initialise register to a 0
jnc now_rotate ; If eax bit was a 0 jump to now_rotate
inc ebx ; Increment register to a 1
now_rotate:
And it is yet easier to initialise to zero by using "xor with itself", which has a shorter encoding than mov ebx, imm32
, and is recognised as a zeroing idiom on modern processors. This clobbers the flags register, which means we cannot put it between the shift and the conditional jump. But we can swap the shift and zeroing to have the zero initialisation first:
xor ebx, ebx ; Initialise register to a 0
shr eax, 0x1 ; Kick the right-most bit out ...
jnc now_rotate ; If eax bit was a 0 jump to now_rotate
inc ebx ; Increment register to a 1
now_rotate:
Below your label now_rotate you shift the single bit into a mask to OR into the destination register. I shift the destination register by one place in each iteration instead. Your way uses an additional register -- this is of course more of an issue for my 16-bit implementation that runs out of registers sooner. The additional shifting of the single bit into a mask, needing an up-to-31-places shift, and applying that mask to the destination would also be much more complex with 16-bit registers than my solution's double-width one-bit shift.
Your loop also shifts the source register to the right one place in each iteration, shifting a bit of interest into the Carry Flag. This is the same as in my solution. It would also be valid to shift to the left and shift the MSB into the Carry Flag, then rotate-with-carry-right that into the MSB of the destination register. The way we chose is easier to handle for arbitrary width bit mirroring though.
ch
register is initially zero. Does the Windows ABI guarantee this? \$\endgroup\$