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Dec 10, 2019 at 15:41 comment added Roland Illig @ecm Thanks for the edit and for suggesting shr instead of rcr. Indeed, when I looked up the latency and throughput for the rcr reg, 1 instruction, I was surprised that it is not always 1 cycle and 1 latency, even though this instruction can be implemented by just routing some wires.
S Dec 10, 2019 at 15:39 history suggested ecm CC BY-SA 4.0
fix adc spelling (not addc), change rcr and rcl to include the count of 1
Dec 10, 2019 at 15:38 comment added ecm shr eax, 1 like in the original would work instead of rcr eax, 1 -- though the resulting value in eax would be discarded anyway so it doesn't matter much.
Dec 10, 2019 at 15:36 review Suggested edits
S Dec 10, 2019 at 15:39
Dec 10, 2019 at 10:20 history edited Roland Illig CC BY-SA 4.0
added 1391 characters in body
Jun 27, 2017 at 16:28 vote accept michael.zech
Jun 26, 2017 at 20:26 history answered Roland Illig CC BY-SA 3.0