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Josh
  • Member for 9 years, 3 months
  • Last seen more than 7 years ago
  • Syracuse, NY
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About

Digital/FPGA Engineer with a side of software.

Interests also in areas of networking, virtualization, and data storage.

BS Computer Engineering - Clarkson University, Potsdam, NY, USA

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Top posts
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Efficiently concatenate substrings of long list of strings
Sep 3, 2015
Top network posts
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28
Multidimensional Array Of Signals in VHDL
23
Is there a reason to initialize (not reset) signals in VHDL and Verilog?
20
Is it possible to create several instances of the same component using a loop?
19
shift a std_logic_vector of n bit to right or left
16
When must a signal be inserted into the sensitivity list of a process