Staff Verification Engineer with over 10 years of professional experience, plus RTL implementation and schematic experience. When I'm not resolving bugs, I'm finding ways maximize quality of the design, streamline verification, and teaching other best practices. Other skills on my tool belt: C, C++, Perl, GNUmakefile.
I am a advocate of system-verilog because it gives flexibility for verification and enforces best practices for RTL design. Quality design can be done with only verilog, however system-verilog will catch basic design bugs and syntheses surprises early (e.g. transparent latches, multiple drivers on nets, procedural when intending parallel logic).
Mission on StackOverflow (and Other StackExchange sites)
- Help others
- Promote best practices
- Learn something new
- SystemVerilog LRM IEEE Std 1800-2017 (includes legacy Verilog)
- UVM LRM IEEE Std 1800.2-2017
- Cliff Cummings Papers, Sunburst Design
- Stuart Sutherland Papers, Sutherland HDL
- Doulos Guide to SV
- EDA Playground (online simulator)
- UVM (Manual, User Guild, & Code)