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1

Have I made any rookie mistakes or committed major sins against Verilog style? Overall it is coded very well and easy to read, no Verilog sins (unlikely to synthesize if there were). Clean Verilog-2001 syntax utilizing ANSI style header and @*. The only potential error I could spot (without building a testbench) is with f_pc, regs, e_*, and most d_* ...


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Why are the inputs signed, are you working with negative dimensions? Most FPGAs have dedicated logic for multiplication so you usually can simply write x*y without having any issues. For better or worse, manually writing it out like you did could impact optimization. Be aware your multiply truncates most of the MSB bits. An 8-bit times 8-bit input would ...


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If you had ran simulation or loaded onto FPGA, you would noticed you didn't get the expected behavior. Run simulation and look at waveforms before loading to FPGA. You have hcnt <= hcnt + 1; at the bottom of your always block, this will override hcnt <= 0; which is not what you want. <= is a non-blocking assignment which means it will be evaluated ...


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