With this algorithm I update an automatically generated verilog-file. The update within this file are done by commenting the assigned wires to specific ports of module instances.
Is there a better, more elegant or more optimized way to do this than with this algorithm?
file_name = "test.v" # name of the verilog file
test = ".test" # port name 1
tezt = ".tezt" # port name 2
dummy = [] # buffer for the updated string
with open(file_name, "r+") as f:
lines = f.readlines()
f.seek(0)
f.truncate() # clear the file
for line in lines:
if test in line or tezt in line: # check if one of the ports is in the line
if line[line.index('(')+1] != '/': # check if the assigned wire is already is commented
for c in line: # update the line and comment the wire name within the brackets
if c == ')':
dummy.append("*/")
dummy.append(c)
if c == '(':
dummy.append("/*")
line = line.replace(line, "".join(dummy)) # replace the old line with the new string
dummy.clear()
f.write(line)
f.close()
```