Questions tagged [vhdl]

VHDL (Very High Speed Integrated Circuit HDL) is a hardware description language (HDL) maintained by the 'VHDL Analysis and Standardization Group (VASG) and standardized as 'IEEE Standard 1076'.

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Q: Efficient modular arithmetic in VHDL

I'm building some modules in VHDL for handling modular arithmetic and want to make sure it's well-designed for timing and somewhat efficient when scaling up. This will need to work with 128-bit or 256-...
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1answer
1k views

CPU's Control Unit in VHDL

I have designed the Control Unit of the CPU in VHDL. It works properly and produces the expected simulation waveforms. Nevertheless, I feel that my existing code can be improved considerably. My ...
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1answer
106 views

D-flop with enable and clear, translated from VHDL to Haskell

I am in the process of translating an implementation of dflop_en_clr from VHDL to Haskell: ...
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1answer
120 views

Sum of switch-triggered integers in VHDL

I've implemented a VHDL program that sums up the positions of switches and shows it on a 7-segment LED, but I've had to use lots of temporaries and a division. Is there a better way? ...
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85 views

Adding two binary-coded-decimal numbers

I want to make some VHDL code open source. But before I do, I want to make sure that it is as readable as possible. Things to improve upon could for example be naming and the use of comments. The ...
5
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1answer
348 views

AXI4-Stream module

I'm implementing an AXI4-Stream module. The module uses three DSP blocks (DSP49E1, UG479 - Xilinx). In order to run the module at a frequency of 150 MHz, the design is a pipeline going successively ...
11
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1answer
6k views

16-bit Parity Generator

I have completed a VHDL 16-bit parity generator and I would like to know if I have programmed it correctly. I have compiled it 10 times and worked out any bugs that it found. I was finally able to ...
19
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1answer
6k views

VHDL mux in need of generics

I've built a multiplexer which takes 2 inputs: one array of std_logic_vector and one std_logic_vector to select the correct ...
5
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1answer
3k views

Clock mux for allowing glitch-free muxing of asynchronous clocks

This clock mux is meant to allow glitch-free muxing between asynchronous clocks clk_a and clk_b via a (also asynchronous to both ...
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2answers
9k views

32-bit counter and test bench

How could this VHDL counter and its test bench be improved? I am interested in anything you see that could be done better, but especially in the test bench: Is ...
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2answers
2k views

Simple SPI Master

I wrote a simple SPI Master implementation to send characters to a LCD screen. Only the output is actually implemented in this so there is no rx register. This only sends a character out when write is ...