Questions tagged [verilog]
Verilog is a hardware description language (HDL) maintained by Accellera Systems Initiative and standardized as 'IEEE Standard 1364'.
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Variable output stream delay no shift register
I'm looking to improve my Verilog coding form by reducing utilization and learning any tricks more experienced Verilogers may know.
This module takes in a pulse data stream with pulses occurring ...
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LED matrix controller - Verilog
I'm an ECE student. My experience in Verilog and FPGAs is mainly from my digital logic design class. To practice Verilog, I decided to implement a controller for Adafruit LED matrices. It interfaces ...
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fixed pseudo-random binary sequence (prbs)
On recent comments based fixed modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by ...
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Heart beat RTL module
Heart rate or blink generator. Clocked from the system frequency, but calculated from a constant of 120MHz. Has a prescaler with values 2, 3, 5, 6, for even heart beat / blinking. The IS_DEBUG ...
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pseudo-random binary sequence (prbs)
Modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by transferring the bus to, for ...
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Carry Lookahead Adder - SystemVerilog
I have been learning SystemVerilog before I go back to school and decided to try and implement a Carry Lookahead Adder. As far as I can tell, it works correctly though I haven't tested extensively, ...
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Generate a sine wave
This ip core simply generates a sine wave according a .mem file. It is required to specify rom depth equal to number of the sine points, the init file and the data size contained in the file. The ...
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Finding the carry out of the "+" operator in SystemVerilog
I'm trying to learn digital design this summer and currently going through this excercise of creating a 32-bit ALU based on this schematic:
Im using the + operator ...
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A byte endian swapper
There are both a simple byte endian (little and big) order swapper and its testbench. A data stream inputs to the module and is converted to the other endianness by computational logic.
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Pulse-width modulation module
Module for generating a PWM signal. The req_value_i input gets a duration value of the signal. Furthermore, the module can be stopped by deassertion of the enable_i input.
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AXI stream data generator
A Stream Data Generator which can take data from both a file or just a counter. This is needed for me as a testbench component for interfaces which works on one hand as an AXIS slave and on the other ...
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Parameterized Verilog shift register code
I am a beginner in FPGAs, and I am studying Verilog HDL. Could you please check the quality of my code (a shift register)? Any comments are welcome.
The shift register serializes parallel from ...
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Range checking function
Here is the problem: Verilog code and testbench for detecting the range of the input given number. If input number is between 12 to 49 then output is '1' else '0'. Range should be easily programmable.
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3-way multiplexer built on 2-way multiplexers in Verilog
I created this project on EDA Playground that builds a variable-width 3-way multiplexer out of 2 variable-width 2-way multiplexers. It will be part of homework that I assign, so I want to follow all ...
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Full Adder in Verilog
I'll be teaching Computer Architecture at the undergraduate level this fall and want to make sure that my example Verilog code follows best practices. I welcome any suggestions, however minor, for ...
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VGA sync generator for 640x480@60Hz
I wrote my first module in Verilog. The purpose is to maintain two counters and emit signals corresponding to VGA's HSync and VSync, as well as HBlank and VBlank pulses to be used by a video ...
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Verilog implementation of trapezoidal integration method
Any and all comments are welcome in this review.
Problem
I've been doing a lot with numerical integration methods recently and have mostly been programming in Python. But...speedups! And FPGAs are ...
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Simple SystemVerilog AXI controller
I have more long term project I'm using to learn FPGA/HDL and this is first sub-sub-sub component of it used for testing ;) I'm targeting Zynq device.
I'd like to create a component which create an ...
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8-Bit ALU in Verilog
I'm an EE student who's taken a a couple digital logic/design courses, but they were focused on schematic representation, so I'm teaching myself Verilog to implement what I've learned.
For a basic ...
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32-bit ALU design implementation and testbench
This is 32bit ALU with a zero flag,
F2:0 Function
000 A AND B
001 A OR B
010 A + B
011 not used
100 A AND B
101 A OR B
110 A − B
111 SLT
SLT is set less ...
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Haskell Parsec parser of Verilog-style number literals
I've set myself the task to write a function that parses Verilog-style number literals. In Verilog, numbers are written like this:
8'b10101100, ...
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Divide a clock signal by 8
I'm a fresh verilog / HDL programmer and I'm writing this post to get some feedback from more experienced verilog / HDL programmers.
My very first task was to divide a clock by eight.
I know there ...
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Verilog UART Transmitter
This is one of the first Verilog programs I have written. I have a Xilinx Artix-7 FPGA card. Right now I just have it transmitting an "X" every second. It works and I can see the result in my serial ...
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4-stage pipelined RV32I CPU in Verilog
This is a simple 4-stage pipeline that partially implements the RV32I ISA.
All instructions are supported, except jalr, those relating to memory (...
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ALU design for a 16-bit microprocessor
I'm having a hard time figuring out if the code I wrote is purely combinatorial or sequential logic. I'm designing a simple 16-bit microprocessor (will be implemented on a Spartan 6) and I'm new to ...
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Implementation of interface within state machine
This particular example is verilog, but my question is more about the state machine structuring, which would be relevant to both VHDL and verilog.
So if I have a state machine, this one is fairly ...
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