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Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

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3 votes
1 answer
63 views

Detect when X-axis inputs and Y-axis inputs go high

I am working on a module named PinCoordinates that detects when X-axis and Y-axis inputs go high. This will be programmed onto an Altera MAX V CPLD. I am ...
Brandon Higgs-Carr's user avatar
1 vote
1 answer
175 views

ROM memory in SystemVerilog and cocotb

The Verilog module describes a ROM memory. An initialization file is needed for the INIT_FILE parameter. Below are Makefile, gtkwave.tcl to launch gtkwave, ...
Artem Shimko's user avatar
1 vote
1 answer
91 views

Clock frequency meter module

The module measures input clocks. It requires some reference clock. There can be from one to five input clocks to measure it. Output values are usual unsigned ones. As expected, it should be reset ...
Artem Shimko's user avatar
2 votes
1 answer
235 views

SystemVerilog implementation of an N-bit prefix adder logic design

I want some feedback about my code (anything is welcome). It is working, but it feels like a clumsy implementation. Because I am self-learning from a book without an answers section, it becomes ...
Miguel Ortega's user avatar
4 votes
2 answers
442 views

Simple GPIO design module in SystemVerilog

I am designing a very crude general-purpose input/output (GPIO) module to provide IO pin control to a RISC-V (like) architecture microprocessor I am currently playing with. This is the code so far: <...
ExpL0siV3Man79's user avatar
3 votes
2 answers
978 views

Accessing multiple dynamic libraries with the same extern C methods

I have multiple pre-compiled dynamic libraries that use the same extern "C" function names. The functions can behave differently for each dynamic library. ...
Greg's user avatar
  • 443
1 vote
1 answer
142 views

fixed pseudo-random binary sequence (prbs)

On recent comments based fixed modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by ...
Drakonof's user avatar
  • 423
3 votes
1 answer
322 views

Heart beat RTL module

Heart rate or blink generator. Clocked from the system frequency, but calculated from a constant of 120MHz. Has a prescaler with values 2, 3, 5, 6, for even heart beat / blinking. The IS_DEBUG ...
Drakonof's user avatar
  • 423
2 votes
1 answer
2k views

pseudo-random binary sequence (prbs)

Modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by transferring the bus to, for ...
Drakonof's user avatar
  • 423