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Questions tagged [hdl]

HDL stands for hardware description language. The most common examples are VHDL and verilog.

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3 votes
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SPI prototype in Verilog: areas for code improvement

I'm working on an SPI in Verilog. I will post what I came up with here. This is an educational project compiled according to the general principle from Wikipedia. There is only one mode - exchange ...
ayr's user avatar
  • 133
3 votes
1 answer
67 views

Detect when X-axis inputs and Y-axis inputs go high

I am working on a module named PinCoordinates that detects when X-axis and Y-axis inputs go high. This will be programmed onto an Altera MAX V CPLD. I am ...
Brandon Higgs-Carr's user avatar
4 votes
1 answer
124 views

Design and stimulus for a simple Mealy finite state machine

I am trying to code a state machine for the given state diagram: I ...
Ervin Ranjan's user avatar
2 votes
1 answer
240 views

SystemVerilog implementation of an N-bit prefix adder logic design

I want some feedback about my code (anything is welcome). It is working, but it feels like a clumsy implementation. Because I am self-learning from a book without an answers section, it becomes ...
Miguel Ortega's user avatar
4 votes
1 answer
650 views

LED matrix controller - Verilog

I'm an ECE student. My experience in Verilog and FPGAs is mainly from my digital logic design class. To practice Verilog, I decided to implement a controller for Adafruit LED matrices. It interfaces ...
hjkl's user avatar
  • 123
2 votes
1 answer
2k views

pseudo-random binary sequence (prbs)

Modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by transferring the bus to, for ...
Drakonof's user avatar
  • 433
3 votes
1 answer
2k views

Carry Lookahead Adder - SystemVerilog

I have been learning SystemVerilog before I go back to school and decided to try and implement a Carry Lookahead Adder. As far as I can tell, it works correctly though I haven't tested extensively, ...
Carson's user avatar
  • 193
5 votes
2 answers
1k views

Generate a sine wave

This ip core simply generates a sine wave according a .mem file. It is required to specify rom depth equal to number of the sine points, the init file and the data size contained in the file. The ...
Drakonof's user avatar
  • 433
3 votes
1 answer
100 views

Pulse-width modulation module

Module for generating a PWM signal. The req_value_i input gets a duration value of the signal. Furthermore, the module can be stopped by deassertion of the enable_i input. ...
Drakonof's user avatar
  • 433
3 votes
1 answer
600 views

Parameterized Verilog shift register code

I am a beginner in FPGAs, and I am studying Verilog HDL. Could you please check the quality of my code (a shift register)? Any comments are welcome. The shift register serializes parallel from ...
Drakonof's user avatar
  • 433
6 votes
1 answer
797 views

VGA sync generator for 640x480@60Hz

I wrote my first module in Verilog. The purpose is to maintain two counters and emit signals corresponding to VGA's HSync and VSync, as well as HBlank and VBlank pulses to be used by a video ...
robbie's user avatar
  • 261
5 votes
1 answer
2k views

Simple SystemVerilog AXI controller

I have more long term project I'm using to learn FPGA/HDL and this is first sub-sub-sub component of it used for testing ;) I'm targeting Zynq device. I'd like to create a component which create an ...
Maja Piechotka's user avatar
6 votes
1 answer
8k views

8-Bit ALU in Verilog

I'm an EE student who's taken a a couple digital logic/design courses, but they were focused on schematic representation, so I'm teaching myself Verilog to implement what I've learned. For a basic ...
supershirobon's user avatar
1 vote
1 answer
8k views

32-bit ALU design implementation and testbench

This is 32bit ALU with a zero flag, F2:0 Function 000 A AND B 001 A OR B 010 A + B 011 not used 100 A AND B 101 A OR B 110 A − B 111 SLT SLT is set less ...
u185619's user avatar
  • 815
8 votes
1 answer
7k views

Verilog UART Transmitter

This is one of the first Verilog programs I have written. I have a Xilinx Artix-7 FPGA card. Right now I just have it transmitting an "X" every second. It works and I can see the result in my serial ...
chasep255's user avatar
  • 225
7 votes
1 answer
320 views

Implementation of interface within state machine

This particular example is verilog, but my question is more about the state machine structuring, which would be relevant to both VHDL and verilog. So if I have a state machine, this one is fairly ...
stanri's user avatar
  • 173
14 votes
2 answers
12k views

32-bit counter and test bench

How could this VHDL counter and its test bench be improved? I am interested in anything you see that could be done better, but especially in the test bench: Is ...
Wayne Conrad's user avatar
  • 3,274
2 votes
2 answers
3k views

Simple SPI Master

I wrote a simple SPI Master implementation to send characters to a LCD screen. Only the output is actually implemented in this so there is no rx register. This only sends a character out when write is ...
smithch's user avatar
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