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Questions tagged [fpga]

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing.

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3 votes
1 answer
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SPI prototype in Verilog: areas for code improvement

I'm working on an SPI in Verilog. I will post what I came up with here. This is an educational project compiled according to the general principle from Wikipedia. There is only one mode - exchange ...
ayr's user avatar
  • 133
3 votes
1 answer
67 views

Detect when X-axis inputs and Y-axis inputs go high

I am working on a module named PinCoordinates that detects when X-axis and Y-axis inputs go high. This will be programmed onto an Altera MAX V CPLD. I am ...
Brandon Higgs-Carr's user avatar
4 votes
1 answer
125 views

Design and stimulus for a simple Mealy finite state machine

I am trying to code a state machine for the given state diagram: I ...
Ervin Ranjan's user avatar
1 vote
1 answer
92 views

Clock frequency meter module

The module measures input clocks. It requires some reference clock. There can be from one to five input clocks to measure it. Output values are usual unsigned ones. As expected, it should be reset ...
Artem Shimko's user avatar
4 votes
1 answer
650 views

LED matrix controller - Verilog

I'm an ECE student. My experience in Verilog and FPGAs is mainly from my digital logic design class. To practice Verilog, I decided to implement a controller for Adafruit LED matrices. It interfaces ...
hjkl's user avatar
  • 123
1 vote
1 answer
148 views

fixed pseudo-random binary sequence (prbs)

On recent comments based fixed modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by ...
Drakonof's user avatar
  • 433
3 votes
1 answer
330 views

Heart beat RTL module

Heart rate or blink generator. Clocked from the system frequency, but calculated from a constant of 120MHz. Has a prescaler with values 2, 3, 5, 6, for even heart beat / blinking. The IS_DEBUG ...
Drakonof's user avatar
  • 433
2 votes
1 answer
2k views

pseudo-random binary sequence (prbs)

Modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by transferring the bus to, for ...
Drakonof's user avatar
  • 433
3 votes
1 answer
2k views

Carry Lookahead Adder - SystemVerilog

I have been learning SystemVerilog before I go back to school and decided to try and implement a Carry Lookahead Adder. As far as I can tell, it works correctly though I haven't tested extensively, ...
Carson's user avatar
  • 193
2 votes
0 answers
383 views

a simple interrupt polling program due to AXI DMA IP

The program transfers a data array from a Zynq-7000 PS DDR to a BRAM IP (block RAM) memory in a PL part of a FPGA due to a PL AXI DMA IP. Inferring a xilinx axi dma driver (not scatter-gather mode), ...
Drakonof's user avatar
  • 433
6 votes
1 answer
797 views

VGA sync generator for 640x480@60Hz

I wrote my first module in Verilog. The purpose is to maintain two counters and emit signals corresponding to VGA's HSync and VSync, as well as HBlank and VBlank pulses to be used by a video ...
robbie's user avatar
  • 261
7 votes
1 answer
116 views

Signal output on Raspberry Pi that acts as input for FPGA

Problem I'm writing a verilog program that does the trapezoidal integration method (where a review is also welcome, wink wink). But turns out you need input for these kind of things, so in the overly ...
auden's user avatar
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6 votes
1 answer
1k views

Verilog implementation of trapezoidal integration method

Any and all comments are welcome in this review. Problem I've been doing a lot with numerical integration methods recently and have mostly been programming in Python. But...speedups! And FPGAs are ...
auden's user avatar
  • 431
5 votes
1 answer
2k views

Simple SystemVerilog AXI controller

I have more long term project I'm using to learn FPGA/HDL and this is first sub-sub-sub component of it used for testing ;) I'm targeting Zynq device. I'd like to create a component which create an ...
Maja Piechotka's user avatar
6 votes
1 answer
8k views

8-Bit ALU in Verilog

I'm an EE student who's taken a a couple digital logic/design courses, but they were focused on schematic representation, so I'm teaching myself Verilog to implement what I've learned. For a basic ...
supershirobon's user avatar
5 votes
1 answer
1k views

AXI4-Stream module

I'm implementing an AXI4-Stream module. The module uses three DSP blocks (DSP49E1, UG479 - Xilinx). In order to run the module at a frequency of 150 MHz, the design is a pipeline going successively ...
Marmoz's user avatar
  • 151
5 votes
2 answers
376 views

FIR filters in C

I wrote 2 filters in C for the Altera DE2 Nios II FPGA, one floating-point and one fixed-point. I've verified that they perform correctly and now I wonder if you can give examples for improvement or ...
Niklas Rosencrantz's user avatar
1 vote
1 answer
709 views

Hardware interrupts for Nios 2

The program is behaving like expected, but I think something better can be done since I'm a novice C programmer. I suspect that the interrupt handler can use some other way of calling the hardware ...
Niklas Rosencrantz's user avatar
3 votes
2 answers
665 views

Polling for Nios 2

The program listens to the Altera FPGA DE2 board's keys that can start and stop and reset a counter: ...
Niklas Rosencrantz's user avatar