I have created a clock divider that works as follows:
- If the division factor is 0, pass the clock through unchanged.
- Otherwise, flip the output clock signal after the specified number of input clock cycles has passed.
I am relatively new to hardware design, so I would like advice on general best practices that I may have violated, as well as whether there would be any robustness issues. (I know that the output clock will be delayed since it passes through gates, but I don't think this is a problem as long as downstream logic does not attempt to use both clocks simultaneously.)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity config_clk_div is Port ( clk : in STD_LOGIC; divfactor : in STD_LOGIC_VECTOR (15 downto 0); clkout : out STD_LOGIC); end config_clk_div; architecture Behavioral of config_clk_div is signal clk_counter : UNSIGNED(15 downto 0); signal current_clk : STD_LOGIC; begin process (clk, divfactor) is begin if divfactor = x"0000" then clkout <= clk; current_clk <= clk; else if rising_edge(clk) then clk_counter <= clk_counter + 1; if clk_counter >= unsigned(divfactor) then clk_counter <= to_unsigned(1,16); current_clk <= not current_clk; -- Not here as well to avoid lag clkout <= not current_clk; else clkout <= current_clk; end if; end if; end if; end process; end Behavioral;