These are the three steps that need to be taken in order to successfully activate Long Mode. Error reporting is sparse as most real hardware for developing an OS is 64 bit but probably still a good idea to implement this verification procedure.
I did a little tweaking of some of the examples that can be found on the web either in whole or in part and believe 74 bytes might be as tight as it can get.
PageZero equ 0xb800 ID equ 0b100000 ; AMD 24592 Rev 3.14 2007 Feature detection. Section 3.6 pg 74 ; ------------------------------------------------------------ ; A: Test if CPU supports CPUID pushfd ; Save a current copy of flags ; Create a simplified pointer that becomes essentially SS:BX push ss mov bx, sp ; BX will point to bits 23-16 of EFLAGS pop ds ; Read flags, toggle (ID) and write back to flags. pushfd ; Get another copy of EFLAGS or byte [bx], ID ; Toggle bit 21 (ID) [bit 5 of BX] mov al, [bx] ; Save a copy popfd ; Write value back to EFLAGS ; Read flags again and if ID remains inverted, then processor supports CPUID. pushfd pop dx ; DX = Bits 15 - 0 of EFLAGS pop dx ; DX = Bits 16 - 31 popfd ; Restore flags to original values xor al, dl ; Bit 4 of AL & DL is (ID) jz TstExt ; As this error is very improbable, near center bottom there will be an uppercase "E" ; yellow on red, with two red flashing bars on each side. FncErr: mov di, (22*80+39)*2 ; Point to center position of 21th row in video mov ax, PageZero ; Page 0 of 80x26x16 (Mode 3) mov es, ax mov eax, 0x2e4684b1 ; This makes the desired character combination work stosd stosw cli hlt jmp $ - 1 ; Just hang. ; B: Are extended functions supported TstExt: mov eax, 0x80000000 push eax cpuid ; Extended function limit pop edx cmp eax, edx jb FncErr ; C: Does processor support Long Mode. mov al, 1 ; Set EAX = 0x80000001 cpuid bt edx, 29 ; 64 bit available if bit is on. jnc FncErr