I have an instructor who is very stringent on makefiles only containing rules and dependencies that need to be included.
The structure for the program is very basic. The requirement is to produce two executable files: a3b and a3m. There was some code duplication, so I included that in a source code file called myarray.c (with a header by the same name).
I have already tested the makefile, and everything seems to work. However, can the makefile be cleaner or more accurate (such as removing or adding rules or dependencies)?
The macro names and values were specified by the instructor.
CFLAGS = -g -Wall - Werror CC = gcc LD = gcc PROG1 = a3b PROG2 = a3m PROG3 = myarray OBJ1 = a3b.o OBJ2 = a3m.o OBJ3 = myarray.o all : $(PROG1) $(PROG2) $(PROG3) $(PROG1) : $(OBJ1) $(PROG3) $(LD) $(OBJ1) $(OBJ3) -o $(PROG1) $(PROG2): $(OBJ2) $(PROG3) $(LD) $(OBJ2) $(OBJ3) -o $(PROG2) $(PROG3): $(OBJ3) $(PROG3).h $(LD) $(PROG3).c -c clean : /bin/rm -f *.o a.out $(PROG1) $(PROG2) $(PROG3)