I'm a fresh verilog / HDL programmer and I'm writing this post to get some feedback from more experienced verilog / HDL programmers.
My very first task was to divide a clock by eight.
I know there are some better methods to do this, but as I'm new to HDL this is my first, naive, attempt:
module prescaleMainCLK(CLK, prescaledCLK);
input CLK;
output reg prescaledCLK;
// ''Define'' a 4bit counter, max value: 15
reg [3:0] counter;
initial begin
// Initialise both variables
prescaledCLK <= 0;
counter <= 0;
end
always @ (posedge CLK) begin
// Did the counter reach its end?
if (counter > 7) begin
// Reset the counter
counter <= 0;
// Toggle the prescaled clock output
prescaledCLK <= ~prescaledCLK;
end else begin
// Increment counter
counter <= counter + 1;
end
end
endmodule
The Simulation output (EDAPlayground) is as I expect it to be:
Now I want to know if that code is suitable for real applications or if there are some things I need to reconsider.