Timeline for Parameterized Verilog shift register code
Current License: CC BY-SA 4.0
8 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jan 15, 2021 at 21:00 | history | tweeted | twitter.com/StackCodeReview/status/1350186042134061063 | ||
| Jan 15, 2021 at 20:40 | vote | accept | Drakonof | ||
| S Jan 15, 2021 at 12:50 | history | edited | Stephen Rauch | CC BY-SA 4.0 |
Minor grammar
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| S Jan 15, 2021 at 12:50 | history | suggested | toolic | CC BY-SA 4.0 |
Title that describes code; added beginner tag; minor grammar; code formatting for signal names.
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| Jan 15, 2021 at 12:47 | review | Suggested edits | |||
| S Jan 15, 2021 at 12:50 | |||||
| Jan 15, 2021 at 12:38 | answer | added | toolic | timeline score: 3 | |
| Jan 15, 2021 at 10:35 | history | edited | Drakonof | CC BY-SA 4.0 |
deleted 4 characters in body
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| Jan 15, 2021 at 9:29 | history | asked | Drakonof | CC BY-SA 4.0 |